PROCESSING SYSTEM (PS)
APU Cluster
Cores + L2 + Coherency
Core0
L1I
L1D
NEON
FPU
ETM
Core1
L1I
L1D
NEON
FPU
ETM
Core2
L1I
L1D
NEON
FPU
ETM
Core3
L1I
L1D
NEON
FPU
ETM
L2 Cache
CCI / Coherency
Power/Clocks
AXI Interconnect
DDR Subsystem
QoS
Scheduler
Addr Map
ECC
Peripherals
USB3 DRD
GEM
SD/eMMC
UART
I2C
SPI
GPIO
Timers
AXI-GP
AXI-HP
AXI-HPC
PS↔PL AXI INTERFACES
AXI GP / HPM0_FPD (PS→PL MMIO)32/64/128-bit
AXI GP / HPM1_FPD (PS→PL MMIO)32/64/128-bit
AXI GP / HPM0_LPD (PS→PL MMIO)32/64/128-bit
AXI HP0 (PL→DDR non-coherent)32/64/128-bit
AXI HP1 (PL→DDR non-coherent)32/64/128-bit
AXI HP2 (PL→DDR non-coherent)32/64/128-bit
AXI HP3 (PL→DDR non-coherent)32/64/128-bit
AXI LPD (PL→PS low-power)32/64/128-bit
AXI HPC0 (PL→DDR coherent)32/64/128-bit
AXI HPC1 (PL→DDR coherent)32/64/128-bit
AXI ACP (PL↔APU cache coherent)32/64/128-bit
AXI ACE (PL↔CCI coherency ext.)32/64/128-bit
PROGRAMMABLE LOGIC (PL)
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