RV32IM

riscv32 · 5-stage · live

A teaching model of a RISC-V backend. The target is a classic five-stage pipeline (IF/ID/EX/MEM/WB) with a non-pipelined multiplier and divider, and the kernel language exposes add, subtract, multiply and divide. Every keystroke recompiles all seven passes.

target triple riscv32-unknown-elf
base RV32I + M extension · XLEN 32
args a0–a2 · result a0 · frame sp

Kernel source

ready
Argument values (used by the simulator)
Backend passes
8

C source, LLVM IR, RISC-V assembly, or the whole run as one page.

Everything runs locally in this page — lexer, parser, IR builder, instruction selector, list scheduler, linear-scan allocator, RV32IM encoder, a five-stage timing model and a small ISS. Tab indents, Ctrl/⌘+Enter forces a rebuild.