Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA
Published in IEEE Transactions on Parallel and Distributed Systems, 29(1), 43–55, 2018
This paper addresses two significant limitations in current Signal Flow Graph (SFG) architectural synthesis approaches for FPGA accelerators: the inability to efficiently utilize programmable datapath components and the lack of automatic derivation of accelerators to meet specific throughput or latency requirements. The authors propose a novel synthesis approach that derives software-programmable multi-core Single Instruction, Multiple Data (SIMD) accelerators from SFG models, incorporating offline characterization of multicore performance and compile-time program analysis to meet prescribed throughput requirements.
Key contributions include:
Multi-SIMD Architecture: Development of an architectural synthesis approach that leverages programmable datapath components in modern FPGAs to create multi-core SIMD accelerators.
Performance Estimation: Introduction of offline performance estimation techniques to predict the performance of the synthesized accelerators and ensure they meet specified throughput requirements.
Case Study: Application of the proposed approach to the design of transceivers for 802.11n WiFi, demonstrating the effectiveness of the synthesis technique in achieving real-time performance.
Recommended citation: Wu, Y., & McAllister, J. (2018). Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA. *IEEE Transactions on Parallel and Distributed Systems, 29*(1), 43–55. https://doi.org/10.1109/TPDS.2017.2753038
Download Paper | Download Slides | Download Bibtex