Efficient co-approximate parallel compressive depth reconstruction on FPGA
Published in ICASSP 2025 (IEEE International Conference on Acoustics, Speech, and Signal Processing), 2025
Depth image reconstruction from sparse samples is essential for machine perception applications (robotics, autonomous vehicles, etc.), especially under tight power, speed, and resource constraints. This paper presents a co-approximate parallel compressive depth reconstruction engine on FPGA that leverages:
- ℓ₁ solvers (proximal gradient descent),
- instrumented frequency and voltage scaling during iterative optimization, and
- multiple parallel approximate processing units.
By exploring different numbers of parallel processing units and approximation levels, the design achieves: ~51% extra power savings, ~421% speed-up over a nominal configuration, yielding over 43× efficiency improvement.
Recommended citation: Wu, Y. & McAllister, J. (2025). “Efficient co-approximate parallel compressive depth reconstruction on FPGA.” In *2025 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2025: Proceedings)*. IEEE.
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