Energy Efficient Reconfigurable Accelerator for Monocular Underwater Image Enhancement
Published in IEEE/ACM 39th IEEE International System-on-Chip Conference 2026, 2026
Image enhancement is crucial for precise underwater visual perception, while deep learning (DL) techniques outperform conventional approaches in diverse environments. However, the deployment of energy-efficient DL inference on autonomous underwater vehicles (AUVs) remains challenging due to strict space and power constraints. This paper presents a hardware- software co-design for real-time underwater image enhancement on an FPGA. A low-power image enhancement accelerator is implemented using a hardware-friendly activation function and employing a lightweight neural network through an automated High-Level Synthesis (HLS) toolchain with extended functionalities. Experimental results demonstrate that the implemented FPGA accelerator delivers exceptional real-time performance and energy efficiency, achieving a significant speedup and ∼ 60% less power consumption compared to a high-performance edge computing platform, and complete co-design framework of deep learning- based underwater image enhancement targeting automated FPGA accelerator generation for edge deployment.
Recommended citation: Qihang Liu, Ziyang Hong, Junfeng Wu, Yuzhe Li, Yun Wu. (2026). "Energy Efficient Reconfigurable Accelerator for Monocular Underwater Image Enhancement." IEEE International System-on-Chip Conference 2026: Proceedings. IEEE.
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