High Performance Real-Time Pre-Processing for Fixed-Complexity Sphere Decoder
Published in 2013 IEEE Global Conference on Signal and Information Processing (GlobalSIP), pp. 1250–1253, 2013
This paper addresses the challenge of real-time pre-processing in Fixed-Complexity Sphere Decoders (FSD) for Multiple-Input Multiple-Output (MIMO) systems. The authors propose an FPGA-based architecture that reorganizes the ordering and QR decomposition sub-operations to reduce resource cost by 50% while maintaining real-time performance.
Key contributions include:
FPGA-Based Architecture: Development of an FPGA-based pre-processing architecture that enhances efficiency in FSD applications.
Resource Optimization: Achieving a 50% reduction in resource cost compared to state-of-the-art solutions.
Real-Time Performance: Ensuring real-time performance suitable for 4×4 802.11n MIMO systems.
Recommended citation: Wu, Y., McAllister, J., & Wang, P. (2013). High performance real-time pre-processing for fixed-complexity sphere decoder. In *2013 IEEE Global Conference on Signal and Information Processing (GlobalSIP)* (pp. 1250–1253). IEEE. https://doi.org/10.1109/GlobalSIP.2013.7086073
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