FPGA-based Tabu Search for Detection in Large-Scale MIMO Systems
Published in 2014 IEEE Workshop on Signal Processing Systems (SiPS): Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1–6, 2014
This paper addresses the challenge of efficient detection in large-scale Multiple-Input Multiple-Output (MIMO) systems by proposing an FPGA-based implementation of the Tabu Search algorithm. The authors aim to balance detection performance with computational complexity, making the approach suitable for real-time applications in large-scale MIMO systems.
Key contributions include:
FPGA Implementation: Development of an FPGA-based architecture to accelerate the Tabu Search algorithm, enhancing its applicability in real-time systems.
Performance Evaluation: Assessment of the proposed implementation’s performance in terms of detection accuracy and computational efficiency.
Scalability Analysis: Examination of the scalability of the approach in large-scale MIMO systems, highlighting its potential for high-dimensional data detection.
Recommended citation: Wu, Y., & McAllister, J. (2014). FPGA-based Tabu Search for Detection in Large-Scale MIMO Systems. In *Proceedings of the 2014 IEEE Workshop on Signal Processing Systems (SiPS)* (pp. 1–6). IEEE. https://doi.org/10.1109/SiPS.2014.6986073
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