FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG
Published in Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Proceedings, Lecture Notes in Computer Science, Vol. 9625, pp. 78–90, 2016
This paper addresses the demand for easily programmable, high-performance image processing platforms based on FPGAs. The authors present a novel, high-performance processor—IPPro—and demonstrate its application to the Histogram of Oriented Gradients (HOG) algorithm on a Xilinx Zynq platform. The study identifies and explores various mapping strategies to improve processing efficiency for soft-cores and examines options for creating a division coprocessor.
Key contributions include:
IPPro Processor: Introduction of the IPPro processor, a high-performance soft-core designed for image processing tasks.
Mapping Strategies: Exploration of mapping strategies to enhance processing efficiency for soft-cores.
Division Coprocessor: Investigation of options for creating a division coprocessor to optimize performance.
Performance Validation: Validation of the approach using the HOG algorithm, achieving a performance of 328 frames per second (fps), representing a 146% speed improvement over the original realization and a tenfold reduction in energy consumption.
Recommended citation: Kelly, C., Siddiqui, F. M., Bardak, B., Wu, Y., Woods, R., & Rafferty, K. (2016). FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. In *Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Proceedings* (Vol. 9625, pp. 78–90). Springer. https://doi.org/10.1007/978-3-319-31462-4_7
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