Automatic approximation for 1-Dimensional Feedback-Loop Computations: a PID Benchmark
Published in Sensor Signal Processing for Defence Conference (SSPD 2022), 2022
This paper tackles the problem of precision optimization in implementing PID control loops on hardware. Using affine arithmetic, the authors automatically estimate the minimal required precision (bit-widths) for both floating-point and fixed-point representations (exponent & mantissa or integer & fractional parts). Benchmarks are applied to 1-D feedback-loop (PID) systems. Hardware FPGA implementations show substantial savings: ~62% average reduction in area and ~27% average reduction in power, when compared to using uniform bit widths. The work provides a template for automating accuracy vs resource trade-offs in embedded PID control systems.
Recommended citation: Wu, Y., Zhang, Y., Hamadouche, A., Mota, J. F. C., & Wallace, A. M. (2022). “Automatic approximation for 1-Dimensional Feedback-Loop Computations: a PID Benchmark.” In *2022 Sensor Signal Processing for Defence Conference (SSPD 2022)*. IEEE. DOI:10.1109/SSPD54131.2022.9896191
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