Joint Undervolting and Overclocking Power Scaling Approximation on FPGAs

This paper investigates the combined effects of undervolting and overclocking on FPGA peripherals, specifically focusing on AXI memory access in Xilinx Ultrascale+ heterogeneous MPSoCs. The study aims to identify optimal power-performance trade-offs by experimentally analyzing the impact of these techniques on on-chip memory access. Key findings include:

• Bit-flipping Patterns: Observed fine-grained bit-flipping patterns when voltage and clock frequencies were tuned beyond certain thresholds, indicating potential reliability concerns.
• Bit Error Rate (BER) Analysis: Conducted a comprehensive BER analysis to quantify the probability of bit-flipping under various voltage and frequency settings.
• Guideline Proposal: Proposed a guideline for selecting balanced voltage and frequency settings that minimize power consumption while maintaining acceptable error rates. The research highlights the importance of understanding fault behaviors introduced by approximate computing techniques like undervolting and overclocking, providing valuable insights for designing low-power and secure FPGA-based systems.

Recommended citation: Wu, Y., Mota, J. F. C., & Wallace, A. M. (2022). Joint undervolting and overclocking power scaling approximation on FPGAs. In *Proceedings of the 11th International Conference on Sensor Signal Processing for Defence (SSPD 2022)*. IEEE. https://doi.org/10.1109/SSPD54131.2022.9896229.
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